I finally figure it out why Analog Devices reference design create/generated in Vivado 2014 by script(obviously updated to use new IP's, otherwise it didn't assemble 'Block Design' at all) didn't work. Reason is changes in Xilinx Concat IP, which used in reference design to concatenate interrupt signals from VDMA and I2C IP blocks to Zynq's F2S interrupt bus.
So, now in 2014.1, we got version 2.0 of it and it preserve the order of input signals on the output. Which means we must either change inputs order or change interrupt numbers in DTS.
So, for AD reference design generated in Vivado2014.1 interrupts are:
- AXI_IIC_MAIN - #56.
- AXI_VDMA_0 - #55.
- AXI_IIC_FMC - #59.