Author: d9#idv-tech#com

Just a list of a few new steps required to install and run Vivado, XSDK and Petalinux 2016.2 on Ubuntu 64bit 16.04: In order to run XSDK which can't use default GTK v3 we have to export new environmental variable.

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I recently switch to Linux Kernel 4.4 (from 4.0) for some of my projects and to my no surprise found Xilinx AXI-DMA not working again. This time it complained that it can't find DMA channel: "unable to read dma-channels property"

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Now personal account on GitHub includes unlimited number of private repositories. I didn't expect it at all, but like this move a lot! Way to go guys! Like4 Dislike1

Apparently, free version of Xilinx Vivado tools (WebPACK edition) now include Logic and Serial I/O Analyzer license! Basically, it now includes all features and an equivalent of old Vivado Design Edition + Vivado HLS, but limited for next devices: Artix-7

A small HowTo (and reminder for myself) on how to use Eclipse (Xilinx SDK) to develop, cross-compile and upload Linux kernel modules for Zynq (ARM-based) embedded board using Xilinx SDK and Xilinx Embedded Linux aka Petalinux. But most steps are

Today Xilinx released new Petalinux 2015.4 which is synchronized with Xilnx Vivado and SDK 2015.4. So, now I can finally switch to a latest Vivado and play with Vivado HLS which now included to all Vivado editions including free of

Today Xilinx released an update to its Vivado. New version number is 2015.2 and biggest news to me is that it now supports Ubuntu Linux 14.04 TLS(64-bit). It also have number of bugs fixed, but not much of new features

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Just a short recipe on how to compile 'tslib' and use it with Qt5 on Xilinx Petalinux. At the moment I'm using Ubuntu 14.04 64bit as a host machine, MicroZed 7020 as a target, Xilinx Vivado version 2014.2 and Petalinux

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John Linn posted some interesting material on Linux Device Drivers. It covers basic Linux driver topics in introduction Sessions 1 and 2, UIO drivers in Session 3 and DMA drivers in kernel mode in Session 4. I found all sessions

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Spent couple of my evenings watching this tutorials and found them painfully slow, but very very useful. Unfortunately for me, I'm already passed that point on my "learning curve" of Zynq and AXI4 bus, but still learned quite a few

Yesterday, a new Zynq based SBC/SOM was released. It very similar to MicroZed boards - just without those huge Ethernet/USB connector and added versions with Z7015 and Z7030, which is nice. Ethernet and USB got moved to 3rd 100pin's connector

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I finally received my FLIR One!!! It's kind of expansive, but very cool infra-red camera for IPhone5/5c. Can make still and video. A very nice toy :) It has two sensors/cameras and as I understand one is infra-red and another

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I finally figure it out why Analog Devices reference design create/generated in Vivado 2014 by script(obviously updated to use new IP's, otherwise it didn't assemble 'Block Design' at all) didn't work. Reason is changes in Xilinx Concat IP, which used

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This is step-by-step tutorial on how to build reference design for Analog Devices ADV7511 HDMI encoder used on ZedBoard with PetaLinux 2013.10. It will be mostly based on AD HDL reference design http://wiki.analog.com/resources/fpga/xilinx/kc705/adv7511 and AD Linux drivers wiki page http://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq

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A small, step-by-step tutorial on how to create and package IP. Just as an example, I will create 3-to-8 decoder IP in Xilinx Vivado 2014.1 and connect it to Zynq SPI chip select pins. This is not a Verilog tutorial,

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