Category: Vivado

Xilinx Vivado, XSDK and Petalinux 2016.2 on Ubuntu 16.04

Just a list of a few new steps required to install and run Vivado, XSDK and Petalinux 2016.2 on Ubuntu 64bit 16.04: In order to run XSDK which can't use default GTK v3 we have to export new environmental variable.

Posted in Linux, Ubuntu, Vivado, Xilinx Zynq Tagged with: , ,

Very useful Zynq and AXI bus tutorials.

Spent couple of my evenings watching this tutorials and found them painfully slow, but very very useful. Unfortunately for me, I'm already passed that point on my "learning curve" of Zynq and AXI4 bus, but still learned quite a few

Posted in AXI, Vivado, Zynq

HDMI on ZedBoard with Petalinux update.

I finally figure it out why Analog Devices reference design create/generated in Vivado 2014 by script(obviously updated to use new IP's, otherwise it didn't assemble 'Block Design' at all) didn't work. Reason is changes in Xilinx Concat IP, which used

Posted in HDMI, Linux, PetaLinux, Vivado, Xilinx Zynq, ZedBoard Tagged with: , , , , , , , ,

HDMI on ZedBoard with Petalinux.

This is step-by-step tutorial on how to build reference design for Analog Devices ADV7511 HDMI encoder used on ZedBoard with PetaLinux 2013.10. It will be mostly based on AD HDL reference design http://wiki.analog.com/resources/fpga/xilinx/kc705/adv7511 and AD Linux drivers wiki page http://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq

Posted in HDMI, Linux, MicroZed, PetaLinux, Vivado, Xilinx Zynq, ZedBoard Tagged with: , , , , , , , , ,

Howto create and package IP using Xilinx Vivado 2014.1

A small, step-by-step tutorial on how to create and package IP. Just as an example, I will create 3-to-8 decoder IP in Xilinx Vivado 2014.1 and connect it to Zynq SPI chip select pins. This is not a Verilog tutorial,

Posted in MicroZed, Vivado, Xilinx Zynq, ZedBoard Tagged with: , , , , , , , , ,

New Vivado 2014.1 released.

Exciting news! Yesterday Xilinx released Vivado 2014.1 - promise about 25% faster runtime and 1.5x overall speedup in compile+simulation! Also they added OpenCL kernels and some Linear algebra library to Vivado HLS! But for me more important changes is that

Posted in Vivado, Xilinx Zynq Tagged with: , , , ,

Howto export Zynq peripherals(I2C, SPI, UART and etc) to PMOD connectors of ZedBoard using Vivado 2013.4

This is the small howto describing export of some peripherals on ZedBoard's PMOD connectors. ZedBoard have some, so called, FIXED_IO connections, which is hardwired to DDR memory, QSPI flash memory, Ethernet and etc. It also export Zynq UART1 to J14

Posted in Vivado, Xilinx Zynq, ZedBoard Tagged with: , , , , , , , , , , , , ,
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