Tag: XSDK

Configure and build Qt5, tslib and evtest for ARM (Xilinx Zynq).

Just a short recipe on how to compile 'tslib' and use it with Qt5 on Xilinx Petalinux. At the moment I'm using Ubuntu 14.04 64bit as a host machine, MicroZed 7020 as a target, Xilinx Vivado version 2014.2 and Petalinux

Posted in ARM, Linux, Qt, Zynq Tagged with: , , , , , , , , , , , , , , , , ,

Howto create and package IP using Xilinx Vivado 2014.1

A small, step-by-step tutorial on how to create and package IP. Just as an example, I will create 3-to-8 decoder IP in Xilinx Vivado 2014.1 and connect it to Zynq SPI chip select pins. This is not a Verilog tutorial,

Posted in MicroZed, Vivado, Xilinx Zynq, ZedBoard Tagged with: , , , , , , , , ,

New Vivado 2014.1 released.

Exciting news! Yesterday Xilinx released Vivado 2014.1 - promise about 25% faster runtime and 1.5x overall speedup in compile+simulation! Also they added OpenCL kernels and some Linear algebra library to Vivado HLS! But for me more important changes is that

Posted in Vivado, Xilinx Zynq Tagged with: , , , ,

ZedBoard Linux-FreeRTOS AMP Board Bringup Guide.

One of the many nice features of Xilinx Zynq is ability to run it in Asymmetric MultiProcessing or AMP configuration. Xilinx released version v2013.10 of a UG980(Petalinux Board Bringup) and UG978(Zynq Linux-FreeRTOS AMP) guides for Xilinx ZC702 board. Today I

Posted in Linux, Xilinx Zynq, ZedBoard Tagged with: , , , , , , , , , , , , , , , ,
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