Tag: Zynq

Just a short recipe on how to compile 'tslib' and use it with Qt5 on Xilinx Petalinux. At the moment I'm using Ubuntu 14.04 64bit as a host machine, MicroZed 7020 as a target, Xilinx Vivado version 2014.2 and Petalinux

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John Linn posted some interesting material on Linux Device Drivers. It covers basic Linux driver topics in introduction Sessions 1 and 2, UIO drivers in Session 3 and DMA drivers in kernel mode in Session 4. I found all sessions

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I finally figure it out why Analog Devices reference design create/generated in Vivado 2014 by script(obviously updated to use new IP's, otherwise it didn't assemble 'Block Design' at all) didn't work. Reason is changes in Xilinx Concat IP, which used

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A small, step-by-step tutorial on how to create and package IP. Just as an example, I will create 3-to-8 decoder IP in Xilinx Vivado 2014.1 and connect it to Zynq SPI chip select pins. This is not a Verilog tutorial,

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Exciting news! Yesterday Xilinx released Vivado 2014.1 - promise about 25% faster runtime and 1.5x overall speedup in compile+simulation! Also they added OpenCL kernels and some Linear algebra library to Vivado HLS! But for me more important changes is that

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This is the small howto describing export of some peripherals on ZedBoard's PMOD connectors. ZedBoard have some, so called, FIXED_IO connections, which is hardwired to DDR memory, QSPI flash memory, Ethernet and etc. It also export Zynq UART1 to J14

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Update for Qt 5.3.2: http://blog.idv-tech.com/2014/10/15/building-and-configuring-qt5-tslib-and-evtest-for-arm-xilinx-zynq/. This is a small how-to build latest Qt 5.2.1 for Zynq and use it with PetaLinux 2013.10 projects. I'm using 64 bit Ubuntu 13.10 as a host, with Xilinx Vivado 2013.4 and ZedBoard 'Rev. D'

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While waiting for my custom TFT panel board to be build and Zynq IP created, I'm decided to go ahead and build Qt libraries and start porting application. In order to test my application I need linux video framebuffer of

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