Tag: MIO

Howto create and package IP using Xilinx Vivado 2014.1

A small, step-by-step tutorial on how to create and package IP. Just as an example, I will create 3-to-8 decoder IP in Xilinx Vivado 2014.1 and connect it to Zynq SPI chip select pins. This is not a Verilog tutorial,

Tagged with: , , , , , , , , ,

Howto export Zynq peripherals(I2C, SPI, UART and etc) to PMOD connectors of ZedBoard using Vivado 2013.4

This is the small howto describing export of some peripherals on ZedBoard's PMOD connectors. ZedBoard have some, so called, FIXED_IO connections, which is hardwired to DDR memory, QSPI flash memory, Ethernet and etc. It also export Zynq UART1 to J14

Tagged with: , , , , , , , , , , , , ,
Top
×